Phase locked loops and delay locked loops are routinely used for data communications, frequency synthesis, clock generation, clock recovery, and similar applications. Phase locked loops and delay locked loops are often implemented in integrated circuits and commonly are realized with charge pump techniques.
FIG. 1 shows a block diagram of a typical charge pump based phase locked loop 1. Phase locked loop 1 comprises a phase detector 4, a charge pump 5, a loop filter 7, and a voltage-controlled oscillator 9. Phase locked loop 1 operates to align clock signals in both frequency and phase.
FIG. 2 shows a block diagram of a typical phase detector 4. Phase detector 4 receives two clock signals CLKI and CLKO at terminals 11 and 12 to generate an output pulse on terminal 14 when clock signal CLKI leads clock signal CLKO, and on terminal 15 when clock signal CLKI lags clock signal CLKO.
Phase detector 4 comprises a D flip flop 25, a D flip flop 27, an AND gate 29, a delay block 31 and a delay block 33. D flip flops 25 and 27 are falling edge triggered flip-flops having their D input terminals connected to a logic one voltage level. As a result, at every falling edge on their clock terminals, the D flip flops generate a logic one output signal at their Q output terminals 26 and 28. AND gate 29 resets D flip flops 25 and 27 when the voltages on Q output terminals 26 and 28 are both at a logic one level.
FIG. 2A shows a timing diagram of various voltages within phase detector 4 while in operation. In this example, clock signal CLKI, illustrated by a waveform 36, leads clock signal CLKO, illustrated by a waveform 37. The voltage on Q output terminal 26 rises to a logic one at time t.sub.1 when clock signal CLKI has a falling edge. The voltage at output terminal 14 rises to a logic one after a small delay, .DELTA.t, as illustrated by waveform 38. The voltage on Q output terminal 28 rises to a logic one at time t.sub.2, which resets D flip flops 25 and 27. The voltage at output terminal 14 then falls to a logic zero after a small delay of .DELTA.t from the falling edge of clock signal CLKO. Thus, an output pulse width equal to the phase difference between the falling edges of clock signals CLKI and CLKO is transmitted on output terminal 14 as illustrated by waveform 38. The delay blocks 31 and 33 have a filtering effect that filters out pulses having pulse widths smaller than a minimum pulse width. Because delay block 33 filters out the small pulse generated on Q output node 28 just before the D flip flops 25 and 26 are reset by AND gate 29, no pulse is transmitted on output terminal 15, as illustrated by waveform 39.
Referring back to FIG. 1, charge pump 5 receives the signals at terminals 14 and 15 at its corresponding terminals 16 and 17. Charge pump 5 controls the voltage V.sub.CP at an output terminal 18 by adding charge to output terminal 18, as long as it detects a pulse on terminal 16, and removing charge from output terminal 18, as long as it detects a pulse on terminal 17. To add and remove charge from output terminal 18, a conventional charge pump provides both a charging current source and a discharging current source. Thus, voltage V.sub.CP at output terminal 18 increases when clock signal CLKI leads clock signal CLKO and decreases when clock signal CLKI lags clock signal CLKO.
Loop filter 7 is coupled at its input terminal 19 to output terminal 18 of charge pump 5. Loop filter 7 stabilizes the loop. Voltage-controlled oscillator 9 generates an oscillating output signal at CLKOUT terminal 13 whose frequency is proportional to the voltage at input terminal 20. Thus, when clock signal CLKI leads clock signal CLKO, voltage V.sub.CP increases as described above, which in turn causes voltage-controlled oscillator 9 to increase the frequency of clock signal CLKO. Conversely, when clock signal CLKI lags clock signal CLKO, voltage V.sub.CP decreases, which causes voltage-controlled oscillator 9 to decrease the frequency of clock signal CLKO. The feedback circuit of FIG. 1 thus constantly attempts to align clock signal CLKO with clock signal CLKI in frequency and phase. When the loop is substantially stabilized, clock signals CLKI and CLKO are aligned in frequency and phase and phase locked loop 1 is in the "locked" condition.
A delay locked loop operates in a similar manner to a phase locked loop except that the voltage controlled oscillator is replaced with a voltage controlled delay line. The voltage controlled delay line receives clock signal CLKI and generates clock signal CLKO. The loop adjusts the delay in voltage controlled delay line until clock signals CLKI and CLKO are aligned in phase, which is the stabilized or locked condition.
Charge pump based phase locked loops and delay locked loops have some performance limitations. One such limitation is termed "static phase error". A static phase error is any phase error that exists between clock signals CLKI and CLKO under locked condition. Ideally, under locked condition, no static phase error should exist. However, in practice, circuit imperfections exist which cause a static phase error.
One source of static phase error is phase detector 4. Delay blocks 31 and 33 filter out pulses smaller than the minimum pulse width. Thus, phase differences between CLKI and CLKO must be greater than the minimum pulse width before an output pulse is provided in either output terminal 14 or output terminal 15. Phase errors smaller than the minimum pulse cannot be resolved, thus resulting in static phase error.
Another source of static phase error is the leakage current at output terminal 18 of charge pump 5 which causes changes in voltage V.sub.CP. Ideally, phase detector 4 does not generate any pulse on terminals 14 or 15 under locked condition. However, in practice, leakage current at output terminal 18 charges or discharges voltage V.sub.CP over time. As a result of the increase or decrease in voltage V.sub.CP, the action of phase locked loop 1 causes a change in the phase of clock signal CLKO. In the steady state, a static phase difference between clock signals CLKI and CLKO is introduced to cause charge pump 5 to substantially counteract effects of the leakage current at output terminal 18.
In some implementations, phase detector 4 generates a minimum pulse on each of terminals 14 and 15 of phase detector 4 to compensate for leakage currents in both the charging and discharging current sources in charge pump 5 when phase locked loop 1 is under locked condition. However, although minimum pulses on each of the terminals 14 and 15 compensate to some degree for the leakage current problem, at least four sources of static phase error result.
A first source of static phase error is unequal charge pump current sources. As mentioned above, charge pumps typically use a charging current source to charge output terminal 18 and a discharging current source to discharge output terminal 18. The charging current source and discharging current source are rarely exactly matched because of physical limitations. Thus, when a minimum pulse is forced on each of input terminals 16 and 17 of charge pump 5 under a locked condition, charge will be added or removed from output terminal 18 because the charging and discharging currents are not equal. This change in the charge at output terminal 18 causes a change in the voltage V.sub.CP, which in turn causes phase locked loop 1 to change the phase of clock signal CLKO thereby introducing a static phase error.
A second source of static phase error is unequal switching times. The charging and discharging current sources are selectably coupled to output terminal 18 by switches, which are invariably less than ideal. Switches for the charging and discharging current sources do not have identical switching times because of differences in type, sizes, bias conditions, drive, driver rise time and driver fall time, and other parametric values. Because the switching times of these switches are not identical, the charge transferred between the charging and discharging current sources and terminal 18 are not equal. Thus, charge will be added or removed from output terminal 18 when phase detector 4 forces the minimum pulse on input terminal 16 and input terminal 17 during lock. This change in the charge at output terminal 18 causes a change in voltage V.sub.CP, which in turn causes phase locked loop 1 to change the phase of clock signal CLKO, thereby introducing static phase error.
A third source of static phase error is charge injection from the switches in charge pump 5. Typically, the switches in charge pump 5 are implemented with field effect transistors. Field effect transistors have significant capacitance between each pair of the gate, the source, and the drain terminals. As a result, when the switches become conductive and non-conductive, these switches couple charge into output terminal 18. Because these switches are not identical, each switch will inject a different amount of charge into output terminal 18. This change in charge at output terminal 18 causes a change in voltage V.sub.CP, which in turn causes a change in the phase of clock signal CLKO, thereby introducing static phase error.
A fourth source of static phase error is the ineffectiveness of this compensation scheme. Despite generating a minimum pulse on both input terminal 16 and input terminal 17, the effect of leakage currents may still be present in the resulting circuit thereby causing static phase error as described above.
Another limitation of charge pump based circuits is sensitivity to any noise added to voltage V.sub.CP. Because voltage V.sub.CP controls the phase of clock signal CLKO, any noise added to voltage V.sub.CP will cause phase and frequency disturbances ("jitters") in clock signal CLKO. In many phase locked loop designs, clock signal CLKO is very sensitive to noise because the frequency of clock signal CLKO is designed to vary by a relatively large amount for a small change in voltage V.sub.CP.
Loop filter 7 may be one source of noise on voltage V.sub.CP. A typical loop filter design includes a resistor connected to terminal 19 in series with a capacitor between terminal 19 and GROUND. As stated above, phase detector 4 generates a minimum pulse on each of the charge pump's input terminals 16 and 17. As a result, charge pump 5 adds charge to output terminal 18, and the resistor of loop filter 7 causes an immediate voltage increase on voltage V.sub.CP equal to the product of the resistor value and the current. The voltage increase ceases when the charge on the capacitor reaches the desired change in voltage V.sub.CP. The voltage increase described above is a transient noise of short duration because charge pump 5 only adds charge for a short duration; nonetheless, this momentary voltage jump causes a momentary change in the frequency of clock signal CLKO, thus causing jitter.
Other noise sources include noisy power supplies, cross coupling of signals on nearby conductors, and varying current demand.